FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 556
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FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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Electrical Characteristics
556
Table 17-12. Ultra ATA Timing (Mode 3, Mode 4, Mode 5)
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface (ATA/
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) specification for further details on measuring
Sym
t92b
t96a
t96b
t98a
t98b
t93
t94
t95
t97
t99
ATAPI - 6) specification name.
these timing parameters.
CRC Word Hold Time at
Sender
CRC word valid hold time at
sender (from DMACK#
negation until CRC may
become invalid)
(see Note 2) (Tcvh)
STROBE output released-to-
driving to the first transition
of critical timing (Tzfs)
Data Output Released-to-
Driving Until the First
Transition of Critical Timing
(Tdzfs)
Unlimited Interlock Time
(Tui)
Maximum time allowed for
output drivers to release
(from asserted or negated)
(Taz)
Drivers to assert or negate
(from released) (Tzad)
Ready-to-final-STROBE time
(no STROBE edges shall be
sent this long after negation
of DMARDY#) (Trfs)
Maximum time before
releasing IORDY (Tiordyz)
Minimum time before driving
IORDY
(see Note 2) (Tziordy)
Time from STROBE edge to
negation of DMARQ or
assertion of STOP (when
sender terminates a burst)
(Tss)
Parameter (1)
Mode 3 (ns) Mode 4 (ns) Mode 5 (ns)
20.0
Min
6.2
50
0
0
0
0
Max
10
60
20
Min
6.2
6.7
50
0
0
0
0
Max
10
60
20
Intel
10.0
Min
35
25
50
0
0
0
®
82801DBM ICH4-M Datasheet
Max
10
50
20
Host
Connector
Device
Connector
Sender
Connector
Host
Connector
See Note 2
Device
Connector
Sender
Connector
Device
Connector
Device
Connector
Sender
Connector
Measuring
Location
Figure
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