FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 379

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8.3.11
Intel
®
82801DBM ICH4-M Datasheet
Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
register should be cleared to 0 based on a Power Button Override. The resume well bits are all
cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
31:16
15:14
Bit
13
12
10
11
9
8
7
6
5
4
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to cause a
SCI, and/or wake event. These bits are cleared by RSMRST#.
Reserved
PME_B0_EN — R/W. Enables the setting of the PME_B0_STS bit to generate a wake event and/
or an SCI or SMI#. PME_B0_STS can be a wake event from the S1-M–S4 states, or from S5 (if
entered via SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit
defaults to 0. It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS bit is set
PME_EN — R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be
BATLOW_EN — R/W.
0 = Disable.
1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when
Reserved
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not affected by a
hard reset caused by a CF9h write.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved
TCOSCI_EN — R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN — R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
USB2_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB2_STS bit to generate a wake event. The USB2_STS bit is set
anytime USB UHCI Controller #3 signals a wake event. Break events are handled via the
USB interrupt.
a wake event from the S1-M
button override).
it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event.
anytime USB UHCI Controller #2 signals a wake event. Break events are handled via the
USB interrupt.
PMBASE + 2Ch
(
00000000h
No
Bits 0
Bits 8
ACPI GPE0_BLK + 2)
–
–
7, 12, 16
11, 13
–
15 RTC
–
31 Resume,
–
S4 state or from S5 (if entered via SLP_EN, but not power
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
ACPI
379