FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 236

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.18.4
236
Table 5-90. Enable for SMBALERT#
Table 5-91. Enables for SMBus Slave Write and SMBus Host Events
Table 5-92. Enables for the Host Notify Command
Interrupts / SMI#
The ICH4 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN
bit.
Table 5-91
generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables
are additive, which means that if more than one row is true for a particular scenario then the Results
for all of the activated rows will occur.
Slave Write to Wake/
SMI# Command
Slave Write to
SMLINK_SLAVE_SM
I Command
Any combination of
Host Status Register
[4:1] asserted
SMBALERT#
asserted low
(always
reported in
Host Status
Register, Bit 5)
HOST_NOTIFY_INTREN
(Slave Control I/O
Register, Offset 11h, bit 0)
Event
Event
and
X
0
1
1
Table 5-92
Register, Offset
INTREN (Host
Control I/O
02h, Bit 0)
INTREN (Host Control
I/O Register, Offset
X
X
1
specify how the various enable bits in the SMBus function control the
02h, Bit 0)
SMB_SMI_EN (Host
Configuration Register,
D31:F3:Off40h, Bit 1)
X
X
0
1
1
D31:F3:Offset 40h,
ration Register,
(Host Configu-
SMB_SMI_EN
X
X
0
1
Bit 1)
X
1
0
D31:F3:Offset 40h, Bit1)
Configuration Register,
SMB_SMI_EN (Host
HOST_NOTIFY_WKEN
(Slave Control I/O
Register, Offset 11h, bit 1)
X
X
X
0
1
(Slave Command I/O
Register, Offset 11h,
SMBALERT_DIS
Intel
Bit 2)
X
0
0
X
X
0
1
®
82801DBM ICH4-M Datasheet
Wake generated when asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when in
the S0 state (SMBUS_SMI_STS)
None
Interrupt generated
Host SMI# generated
Interrupt generated
Wake generated
Slave SMI# generated
(SMBUS_SMI_STS)
None
Wake generated
Interrupt generated
Slave SMI#
generated
(SMBUS_SMI_STS)
Event
Result
Result