FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 253

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.19.3
Intel
®
Figure 5-24. AC-Link Powerdown Timing
82801DBM ICH4-M Datasheet
Note: Before entering any low-power mode where the link interface to the codec is expected to be
AC-Link Low Power Mode
The AC-link signals can be placed in a low-power mode. When the AC ’97 Powerdown Register
(26h), is programmed to the appropriate value, both AC_BIT_CLK and AC_SDIN will be brought
to, and held at a logic low voltage level.
AC_BIT_CLK and AC_SDIN transition low immediately after a write to the Powerdown Register
(26h) with PR4 enabled. When the AC ’97 controller driver is at the point where it is ready to
program the AC-link into its low-power mode, slots 1 and 2 are assumed to be the only valid
stream in the audio output frame.
The AC ’97 controller also drives AC_SYNC, and AC_SDOUT low after programming AC ’97 to
this low power, halted mode
Once the codec has been instructed to halt AC_BIT_CLK, a special wake up protocol must be used
to bring the AC-link to the active mode since normal output and input frames cannot be
communicated in the absence of AC_BIT_CLK. Once in a low-power mode, the ICH4 provides
three methods for waking up the AC-link; external wake event, cold reset and warm reset.
powered down while the rest of the system is awake, the software must set the “Shut Off” bit in the
control register.
Note: AC_BIT_CLK not to scale
AC_BIT_CLK
AC_SDOUT
AC_SYNC
AC_SDIN
prev. frame
prev. frame
slot 12
slot 12
TAG
TAG
Write to
0x20
Data
PR4
Functional Description
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