FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 405

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

10.1.9
10.1.10
.
10.1.11
.
Intel
®
82801DBM ICH4-M Datasheet
MLT — Master Latency Timer Register (IDE—D31:F1)
Address Offset:
Default Value:
PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)
Address Offset:
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
PCNL_BAR—Primary Control Block Base Address Register
(IDE—D31:F1)
Address Offset:
Default Value:
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:16
31:16
15:3
7:0
Bit
15:2
2:1
Bit
Bit
0
1
0
Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitrated as a PCI device, so it does not need a Master Latency Timer.
Reserved
Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. his bit is set to one, indicating a request for I/O space.
Reserved
Base Address — R/W. Base address of the I/O space (4 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. This bit is set to one, indicating a request for I/O space.
0Dh
00h
10h
00000001h
14h
00000001h
–
–
13h
17h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
IDE Controller Registers (D31:F1)
RO
8 bits
R/W
32 bits
R/W
32 bits
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