FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 275
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FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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7.1.24
Intel
®
Table 7-3. Data Register Structure
82801DBM ICH4-M Datasheet
Note: The data register is an 8-bit read only register that provides a mechanism for the ICH4’s integrated
PCIDATA — PCI Power Management Data Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
LAN Controller to report state dependent maximum power consumption and heat dissipation. The
value reported in this register depends on the value written to the Data Select field in the PMCSR
register. The power measurements defined in this register have a dynamic range of 0 W to 2.55 W
with 0.01 W resolution, scaled according to the Data Scale field in the PMCSR. The structure of
the Data Register is given in
Bit
7:0
Bit
1:0
Data Select
9–15
0
1
2
3
4
5
6
7
8
State dependent power consumption and heat dissipation data.
Power State — R/W. This 2-bit field is used to determine the current power state of the integrated
LAN Controller, and to put it into a new power state. The definition of the field values is as follows:
00 = D0
01 = D1
10 = D2
11 = D3
E3h
00h
Data Scale
2
2
2
2
2
2
2
2
2
0
Table
7-3.
D0 Power Consumption
D1 Power Consumption
D2 Power Consumption
D3 Power Consumption
D0 Power Dissipated
D1 Power Dissipated
D2 Power Dissipated
D3 Power Dissipated
Common Function Power Dissipated
Reserved
Description
Description
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
Data Reported
RO
8 bits
275
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