MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 1023

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DDR0AD1[15:8]
Reset
Reset
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
24.0.5.59 Port AD1 Data Register 1 (PT1AD1)
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[7:0]. These pins can also be used as general purpose
I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
24.0.5.60 Port AD1 Data Direction Register 0 (DDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures pin PAD[15:8] as either input or output.
Field
W
W
R
R
7–0
DDR0AD115 DDR0AD114 DDR0AD113 DDR0AD112 DDR0AD111 DDR0AD110 DDR0AD19
PT1AD17
7
0
7
0
Data Direction Port AD1 Register 0
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has
read on PTAD10 register, when changing the DDR0AD1 register.
to be set to logic level “1”.
PT1AD16
Figure 24-62. Port AD1 Data Direction Register 0 (DDR0AD1)
0
0
6
6
Figure 24-61. Port AD1 Data Register 1 (PT1AD1)
Table 24-54. DDR0AD1 Field Descriptions
PT1AD15
5
0
5
0
PT1AD14
0
0
4
4
Description
PT1AD13
3
0
3
0
PT1AD12
0
0
2
2
PT1AD11
1
0
1
0
DDR0AD18
PT1AD10
0
0
0
0