MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 184

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 XGATE (S12XGATEV2)
XGATE Semaphore
XGATE Thread
XGATE Debug Mode
XGATE Software Error
Word
Byte
6.1.2
The XGATE module includes these features:
6.1.3
There are four run modes on S12X devices.
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Special XGATE channel that is not associated with any peripheral service request. A Software
Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module.
A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE.
(see 6.4.4/6-204)
A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request.
A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables
the XGATE’s debug features (see 6.6/6-206).
The XGATE is able to detect a number of error conditions caused by erratic software (see
6.4.5/6-205). These error conditions will cause the XGATE to seize program execution and flag an
Interrupt to the S12X_CPU.
A 16 bit entity.
An 8 bit entity.
Data movement between various targets (i.e Flash, RAM, and peripheral modules)
Data manipulation through built in RISC core
Provides up to 112 XGATE channels
— 104 hardware triggered channels
— 8 software triggered channels
Hardware semaphores which are shared between the S12X_CPU and the XGATE module
Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer
Software error detection to catch erratic application code
Run mode, wait mode, stop mode
The XGATE is able to operate in all of these three system modes. Clock activity will be
automatically stopped when the XGATE module is idle.
Freeze mode (BDM active)
Features
Modes of Operation
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor