MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 262

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 XGATE (S12XGATEV2)
LSL
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
262
N:
Z:
V:
C:
LSL RD, #IMM4
LSL RD, RS
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Z
V
Source Form
old
^ RD[15]
C
new
C
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
IMM4
DYA
Logical Shift Left
RD
0
0
n
0
0
0
0
0
0
1
1
Machine Code
RD
RD
0
0
n bits
RS
IMM4
0
0
1
1
0
Freescale Semiconductor
1
1
0
0
LSL
0
0
Cycles
P
P