MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 231

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

BFINSX
Operation
!(RS1[w:0] ^ RD[w+o:o])
Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes
the bits back io RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored.
Using R0 as a RS1, this command can be used to toggle bits.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
BFINSX RD, RS1, RS2
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
w = (RS2[7:4])
o = (RS2[3:0])
V
0
Source Form
—
C
15
15
15
RD[w+o:o];
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
Bit Field Insert and XNOR
TRI
7
0
1
W4
1
5
W4=3, O4=2
1
4
1
3
3
Machine Code
RD
2
O4
Bit Field Insert XNOR
0
0
0
RS1
RS2
RS1
RD
BFINSX
Chapter 6 XGATE (S12XGATEV2)
RS2
1
1
Cycles
P
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