MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 595

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 16
Interrupt (S12XINTV1)
16.1
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module cannot be nested because the XGATE module cannot be interrupted while
processing.
Freescale Semiconductor
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I bit and X bit maskable interrupt requests
A non-maskable unimplemented opcode trap
A non-maskable software interrupt (SWI) or background debug mode request
A spurious interrupt vector request
Three system reset vector requests
Introduction
The HPRIO register and functionality of the XINT module is no longer
supported, since it is superseded by the 7-level interrupt request priority
scheme.
MC9S12XDP512 Data Sheet, Rev. 2.21
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