MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 945

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Routed
PIFP[7:0]
Reset
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling
edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the
corresponding bit in the PIFP register. Writing a “0” has no effect.
Field
23.0.5.46 Port H Data Register (PTH)
Read: Anytime.
Write: Anytime.
Port H pins 7–0 are associated with the SCI4 as well as the routed SPI1 and SPI2.
These pins can be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value
of the port register, otherwise the buffered pin input state is read.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if
the routed SPI2 module is enabled. Refer to SPI section for details.The routed SPI1 function takes
precedence over the general purpose I/O function if the routed SPI1 is enabled. Refer to SPI section
for details.
The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled
7–0
SCI
SPI
W
R
PTH7
Interrupt Flags Port P
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
SS2
7
0
Writing a logic level “1” clears the associated flag.
PTH6
SCK2
0
6
Figure 23-48. Port H Data Register (PTH)
Table 23-44. PIFP Field Descriptions
MOSI2
PTH5
TXD4
5
0
MISO2
RXD4
PTH4
0
4
Description
PTH3
SS1
3
0
PTH2
SCK1
0
2
MOSI1
PTH1
1
0
MISO1
PTH0
0
0