MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 951

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Reset
Reset
23.0.5.55 Port J Input Register (PTIJ)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can be used to detect
overload or short circuit conditions on output pins.
23.0.5.56 Port J Data Direction Register (DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6
(RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will
not change.
The SCI2 forces the I/O state to be an output for each port line associated with an enabled output
(TXD2). It also forces the I/O state to be an input for each port line associated with an enabled input
(RXD2). In these cases the data direction bits will not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
W
associated pin values.
W
R
R
1
DDRJ7
PTIJ7
7
0
7
0
= Unimplemented or Reserved
= Unimplemented or Reserved
DDRJ6
PTIJ6
0
0
6
6
Figure 23-58. Port J Data Direction Register (DDRJ)
Figure 23-57. Port J Input Register (PTIJ)
DDRJ5
PTIJ5
5
0
5
0
DDRJ4
PTIJ4
0
0
4
4
3
0
0
3
0
0
DDRJ2
PTIJ2
0
0
2
2
DDRJ1
PTIJ1
1
0
1
0
DDRJ0
PTIJ0
0
0
0
0