MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 865

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.54 Port J Data Register (PTJ)
Read: Anytime.
Write: Anytime.
Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0 and IIC1, the routed CAN0 modules
and chip select signals (CS0, CS1, CS2, CS3). These pins can be used as general purpose I/O when not
used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
Freescale Semiconductor
Function
Routed
CAN4/
CAN0
PJ[7:0]
PJ[5:4]
Reset
Field
SCI2
IICO
PJ2
7–6
IIC1
5-4
Alt.
2
W
R
TXCAN4
TXCAN0
SCL0
PTJ7
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general
purpose I/O function if the CAN4 module is enabled.
The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured
as open drain outputs. Refer to IIC section for details.
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if
the routed CAN0 module is enabled. Refer to MSCAN section for details.
The IIC1 function (SCL1 and SDA1) takes precedence over the chip select (CS0, CS2) and general purpose I/O
function if the IIC1 is enabled. The chip selects (CS0, CS2) take precedence over the general purpose I/O. If the
IIC1 module takes precedence the SDA1 and SCL1 outputs are configured as open drain outputs. Refer to IIC
section for details.
The chip select function (CS1) takes precedence over the general purpose I/O.
0
7
= Unimplemented or Reserved
RXCAN4
RXCAN0
SDA0
PTJ6
0
6
Figure 22-56. Port J Data Register (PTJ)
Table 22-51. PTJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
SCL1
PTJ5
CS2
0
5
SDA1
PTJ4
CS0
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
0
0
3
PTJ2
CS1
0
2
TXD2
PTJ1
0
1
RXD2
PTJ0
CS3
0
0
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