MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 602

MC9S12XDP512MAG

Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S12XDP512MAG

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant

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Chapter 16 Interrupt (S12XINTV1)
16.3.1.2
Read: Anytime
Write: Anytime
602
Address: 0x0126
XILVL[2:0]
Reset
Field
2–0
W
R
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the DMA interrupts
coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
0
0
7
Figure 16-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Priority
high
low
= Unimplemented or Reserved
0
0
6
XILVL2
0
0
0
0
1
1
1
1
Table 16-3. INT_XGPRIO Field Descriptions
Table 16-4. XGATE Interrupt Priority Levels
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
XILVL1
5
0
0
1
1
0
0
1
1
XILVL0
0
0
4
0
1
0
1
0
1
0
1
Description
Interrupt request is disabled
0
0
3
Priority level 1
Priority level 2
Priority level 3
Priority level 4
Priority level 5
Priority level 6
Priority level 7
Meaning
0
2
XILVL[2:0]
Freescale Semiconductor
0
1
1
0

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