MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 167

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

5.3.2.2
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
ETRIGCH[2:0]
ETRIGSEL
Reset
Field
2–0
W
7
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
1
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3–0 inputs. See the device overview chapter for availability and connectivity of
ETRIG3–0 inputs. If ETRIG3–0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, that means still one of the AD channels (selected by ETRIGCH2–0) is the source for external trigger.
The coding is summarized in
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3–0 inputs
as source for the external trigger. The coding is summarized in
ETRIGSEL
Only if ETRIG3–0 input option is available (see device overview chapter), else ETRISEL is
ignored, that means external trigger source is still on one of the AD channels selected by
ETRIGCH2–0
0
0
0
0
0
0
0
0
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
ETRIGCH2
Table 5-4. External Trigger Channel Select Coding
Figure 5-4. ATD Control Register 1 (ATDCTL1)
0
0
0
0
1
1
1
1
0
0
0
0
1
Table 5-3. ATDCTL1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
Table
ETRIGCH1
X
0
0
1
1
0
0
1
1
0
0
1
1
5-4.
0
0
4
ETRIGCH0
Description
X
0
1
0
1
0
1
0
1
0
1
0
1
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
0
0
3
External trigger source is
Table
ETRIGCH2
5-4.
Reserved
ETRIG0
ETRIG1
ETRIG2
ETRIG3
1
2
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
1
1
1
1
ETRIGCH1
1
1
ETRIGCH0
1
0
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