PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 113
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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B
port 0, time slot 1. The subscriber’s HDLC-data is exchanged via the D-channel with the
SACCO-A. Monitor and C/I-channels are to be handled via the ELIC.
The SACCO-B communicates via a dedicated signaling highway with a non-PBC group
controller. A 4-MHz clock is input as PDC and HDCB.
Port 1 of the ELIC is to be used as active low output. Thus the port should be linked to
pull-up resistors.
Write
3.8.6
In this sample initialization the ELIC is set up to handle a digital IOM-2 subscriber. The
interfaces of the ELIC are shown below:
Figure 54
ELIC
The subscriber uses the ELIC’s CFI-port 0, channel 0 (time slots 0 - 3). The subscriber’s
upstream B
Write
Semiconductor Group
1
-channel. The subscriber’s downstream B
®
Interfaces for Initialization Example
Initialization Example
PCON1 = FF
PORT1 = FF
1
2
-channel is to be switched to PCM-port 0, time slot 5. The subscriber’s
-channel is to be looped back to the subscriber on the downstream
IOM -2
Interface
µP
R
H
H
D Channel
113
SACCO CH-A
SACCO CH-B
B Channels
ARBITER
D Channel
Controlling
2
ELIC
-channel is to be switched from PCM-
EPIC
R
R
ITS05808
Operational Description
PCM
Highway
Signaling
Highway
PEB 20550
PEF 20550
01.96
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