PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 96
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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Note that the time slot selections in upstream direction are completely independent of
the time slot selections in downstream direction.
CFI - PCM Time Slot Assignment
Switching paths 1 and 2 of figure 47 can be realized for a total number of 128 channels
per path, i.e. 128 time slots in upstream and 128 time slots in downstream direction. To
establish a connection, the P writes the addresses of the involved CFI and PCM time
slots to the control memory. The actual transfer is then carried out frame by frame
without further P-intervention.
The switching paths 5 and 6 can be realized by programming time slot assignments in
the control memory. The total number for such loops is limited to the number of available
time slots at the respective opposite interface, i.e. looping back a time slot from CFI to
CFI requires a spare upstream PCM time slot and looping back a time slot from PCM to
PCM requires a spare downstream and upstream CFI time slot.
Time slot switching is always carried out on 8-bit time slots, the actual position and
number of transferred bits can however be limited to 4-bit or 2-bit sub time slots within
these 8-bit time slots. On the CFI-side, only one sub time slot per 8-bit time slot can be
switched, whereas on the PCM-interface up to 4 independent sub time slots can be
switched.
Examples are given in chapter 5.3.
Figure 47
Switching Paths Inside the EPIC
Semiconductor Group
C
F
I
®
-1
5
3
µP Interface
96
EPIC
µP
1
2
R
4
6
ITS05844
Operational Description
P
C
M
PEB 20550
PEF 20550
01.96
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