PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 134
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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DRCS
OFD1..0
DRE
ADSRO
4.6.5
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: If both DRCS and ADSRO are set to logical 1, the PCM-output data are delayed
OFU1..0
URE
Note: If EMOD:ECMD2 is set to ’0’ some restrictions apply to the setting of PCSR
Semiconductor Group
bit 7
DRCS
by two PDC-clock cycles.
DRCS and ADSRO were added to the standard EPIC-1 PCSR register
implemented in the PEB 2055 up to and including version A3.
(see chapter 4.5).
PCM-Clock Shift Register (PCSR)
Double Rate Clock Shift.
0…the PCM-input and output data are not delayed
1…the PCM-input and output data are delayed by one PDC-clock cycle
Offset Downstream bits 1…0, see POFD-register.
Downstream Rising Edge.
0…the PCM-data is sampled with the falling edge of PDC
1…the PCM-data is sampled with the rising edge of PDC
Add Shift Register on Output.
0…the PCM-output data are not delayed
1…the PCM-output data are delayed by one PDC-clock cycle
Offset Upstream bits 1…0, see POFU-register.
Upstream Rising Edge.
0…the PCM-data is transmitted with the falling edge of PDC
1…the PCM-data is transmitted with the rising edge of PDC
OFD1
H
OFD0
DRE
134
ADSRO
read/write
read/write
Detailed Register Description
OFU1
address: 14
address: 28
OFU0
PEB 20550
PEF 20550
bit 0
H
H
URE
01.96
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