PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 85

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

CCHH
1
0
Control Channel Master
The control channel master (CCM) issues the "D-channel available" information in the
control channel as shown in table 13. If a D-channel is not enabled by the arbiter, the
control channel passes the status, stored in the EPIC-1 control memory (C/I, MR). For
correct operation of the arbiter this status bit has to contain the "blocked" information for
all D-channels under control of the arbiter.
If the ASM is in the state "suspended" the arbiter functionality depends on the status of
the Control Channel Master:
The CCM is enabled if AMO:CCHM = ’1’. All subscribers will be sent the "available/
blocked" information (C/I or MR) as programmed in the control memory. However, the
control memory should be programmed as "blocked".
The CCM is disabled if AMO:CCHM = ’0’. All in the DCE-registers enabled subscribers
(DCE = ’1’) will be sent the information "available" (which has a higher priority than the
"blocked" information from EPIC-1).
If the ASM is in the state "full selection" all D-channels are marked to be available
which are enabled in the user programmable DCE-registers. When the user reprograms
a DCE-register this has an immediate effect, i.e. a currently transmitting subscriber can
be forced to abort its message.
If the ASM is in the state "limited selection" the subscribers which are currently
enabled in DCE and DCES get the information "available"; they can access the
D-channel. The DCE/DCES anding is performed in order to allow an immediate
disabling of individual subscribers.
In the state "expect frame" and "receive frame" all channels except one (addressed
by ASTATE4:0) have blocked D-channels. The disabling of the currently addressed
D-channel in DCE has an immediate effect; the transmitter (HDLC-controller in the
subscriber terminal) is forced to abort the current frame.
Depending on the programming of AMO:CCHH the available/blocked information is
coded in the C/I-channel or in the MR-bit.
Table 13
Control Channel Implementation
The CCHM is activated independently of the SACCO-clock mode by programming
AMO:CCHM. Even when the ASM is disabled (clock mode not 3) the CCHM can be
activated. In this case the content of the DCE-registers defines which D-channels are
enabled.
Semiconductor Group
Control via
MR
C/I
85
Available
1
x0xx
Functional Description
Blocked
0
x1xx
PEB 20550
PEF 20550
01.96