PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 41

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

2
2.1
The ELIC integrates the existing Siemens device PEB 2055 (EPIC-1), a two channel
HDLC-Controller (SACCO: Special Application Communication Controller) with a
PEB 2050 (PBC) compatible auto-mode, a D-channel arbiter, a configurable bus
interface and typical system glue logic into one chip. It covers all control functions on
digital and analog line cards and can be combined via IOM-2 interface with layer-1
circuits or special application devices (e.g. ADPCM/PCM-converters). Due to its flexible
bus interface it fits perfectly into Siemens / Intel or Motorola microprocessor
architectures.
2.2
2.2.1
All registers and the FIFOs of the ELIC are accessible via the flexible bus interface
supporting Siemens / Intel and Motorola type microprocessors. Depending on the
register functionality a read, write or read/write access is possible.
The bus interface consists of the following elements
• Data bus, 8-bit wide, AD0-7, D0-7
• Address bus, 8-bit wide, P0.0-0.7, A0-7
• Two chip select lines, CSE and CSS
• Address latch enable, ALE
• Two read/write control lines, RD, DS and WR, R or W
The ALE-line is used to control the bus structure and interface type.
Table 1
Selectable Bus Configurations
ALE
Fixed to
Fixed to ground
Switching
Semiconductor Group
Functional Description
General Functions and Device Architecture
Functional Blocks
Bus Interface
V
DD
Interface
Motorola
Siemens / Intel
Siemens / Intel
Bus Structure
demultiplexed
demultiplexed
multiplexed
41
Pin 9
DS
RD
RD
Functional Description
PEB 20550
PEF 20550
Pin 8
R or W
WR
WR
01.96