PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 185
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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RBC7..0
VN3..0
4.7.27 Receive Channel Capacity Register (RCCR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: In extended transparent mode the width of the time slot has to be n
4.7.28 Version Status Register (VSTR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 80
Semiconductor Group
bit 7
bit 7
RBC7
1
Receive Bit Count.
Defines the number of bits to be received in a time slot in clock mode 2.
Number of bits per time slot = RBC + 1 (1…256 bits/time slot).
SACCO Version Number.
80
81
RBC6
H
H
…version A1.
...version A2 (ELIC V1.3).
H
H
0
RBC5
0
RBC4
0
185
RBC3
write
write
read
read
VN3
address: (Ch-A/Ch-B): 33
address: (Ch-A/Ch-B): 66
address: (Ch-A/Ch-B): 2E
address: (Ch-A/Ch-B): 5C
Detailed Register Description
RBC2
VN2
RBC1
VN1
PEB 20550
PEF 20550
8 bits.
bit 0
bit 0
RBC0
VN0
H
H
H
H
/73
/E6
01.96
H
H
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