PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 156

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Access in demultiplexed P-interface mode:
Writing a logical 1 to a CMDR-register bit starts the respective operation.
ST
TIG
CFR
MFT1..0
MFSO
MFRW
MFFE
4.6.29 Command Register EPIC
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
0
MFFIFO Read/Write.
0… the MFFIFO is ready to be written to.
1… the MFFIFO may be read.
MFFIFO Empty
0… the MFFIFO is not empty.
1… the MFFIFO is empty.
Start Timer.
0… not action. If the timer shall be stopped, the TIMR-register must simply
be written with a random value.
1… starts the timer to run cyclically from 0 to the value programmed in
TIMR:TVAL6..0.
Timer Interrupt Generation.
0… setting the TIG-bit to logical 0 together with the CMDR:ST-bit set to
1… setting the TIG-bit to logical 1 together with CMDR:ST-bit set to logical 1
CIFIFO Reset.
0… no action.
1… resets the signaling FIFO within 2 RCL-periods, i.e. all entries and the
MF-channel Transfer Control Bits 1,0; these bits start the monitor transfer
enabling the contents of the MFFIFO to be exchanged with the subscriber
circuits as specified in MFSAR. The function of some commands depends
furthermore on the selected protocol (OMDR:MFPS). Table 21 summarizes
all available MF-commands.
MF-channel Search On.
ST
logical 1 disables the interrupt generation.
causes the EPIC-1 to generate a periodic interrupt (ISTA:TIN) each time
the timer expires.
ISTA:SFI-bit are cleared.
H
TIG
®
CFR
-1 (CMDR_E)
156
MFT1
write
write
Detailed Register Description
MFT0
address: 1A
address: 0D
MFSO
PEB 20550
PEF 20550
bit 0
H
H
MFFR
01.96