PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 352
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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The following values must be programmed to the PCM and CFI registers of the ELIC and
to the MOD and CFR registers of the MUSAC to obtain the desired PCM and IOM-2
timing:
ELIC
PBNR
POFD
POFU
PCSR
CMD1
CMD2
CBNR
Figure 121
Timing Example to Interconnect the ELIC
PMOD
Semiconductor Group
MUSAC/ELIC
SP/PFS
CLK/PDC
OUT#/TXD#
IN#/RXD#
®
= 0100 0100
= 1111 1111
= 1111 0000
= 0001 1000
= 0100 0101
= 0010 0000
= 1101 0000
= 1111 1111
R
:
TS63, Bit0
TS63, Bit0
B
B
B
B
B
B
B
B
TS0, Bit7
TS0, Bit7
= 44
= FF
= F0
= 18
= 45
= 20
= D0
= FF
H
H
H
H
H
H
H
H
TS0, Bit6
TS0, Bit6
PCM mode 1, single rate clock, PFS
evaluated with falling clock edge, input
selection RxD0 and RxD3, PCM comparison
disabled
512 bits (64 ts) per PCM frame
PFS marks downstream PCM TS0, bit 6
PFS marks upstream PCM TS0, bit 6
PCM data received with falling, transmitted
with rising clock edge
PDC/PFS clock source, PFS evaluated with
falling clock edge, prescaler = 1, CFI mode 0
FC mode 6, double rate clock, CFI data
transmitted with rising, received with falling
clock edge
256 bits (32 ts) per CFI frame
352
®
and the MUSAC
TS0, Bit5
TS0, Bit5
TS0, Bit4
TS0, Bit4
on an IOM
Application Hints
TS0, Bit3
TS0, Bit3
PEB 20550
PEF 20550
ITT08101
®
-2 Line
01.96
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