PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 186

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

FCC4..0
CCHH
CCHM
4.8
4.8.1
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: To avoid arbiter locking, either
SCA
Note: The D-channel arbiter can only be operated with framing control modes 3, 6 and 7.
Semiconductor Group
bit 7
FCC4
a) the state limited selection can be skipped by setting FCC4..0 = 00
b) the FCC4..0 value must be greater than the value described in chapter 2.2.8.3.
D-Channel Arbiter
Arbiter Mode Register (AMO)
Full selection Counter.
The value (FCC4..0 + 1) defines the number of IOM-frames before the arbiter
state machine changes from the state "limited selection" to the state "full
selection", if the ASM does not detect any ’0’ on the remaining serial input
lines (D-channels).
E.g. max. delay = 9 frames
Suspend Counter Activation.
0…the suspend counter controls the arbiter state machine.
1…the suspend counter is disabled (e.g. for control by P).
Control Channel Handling.
The control channel takes place:
0…in the C/I channel
1…in the MR bit (Monitor channel receive bit)
Control Channel Master activation.
0…disables the control channel master.
1…enables the control channel master.
FCC3
When disabled, all channels enabled in the DCE0-3 registers are sent the
"available" information even when the SACCO-A is currently not
available.
During reception of D-channel data from a channel which has been
enabled in the DCE0-3 registers all other enabled channels are sent the
"blocked" information from the Control Memory (CM).
H
FCC2
FCC1
AMO:FCC4..0 = 01000.
186
FCC0
read/write
read/write
Detailed Register Description
SCA
address: 60
address: C0
CCHH
PEB 20550
H
PEF 20550
, or
bit 0
H
H
CCHM
01.96