PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 216
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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Figure 67
ELIC
CFI Clock Source Prescaler CMD1:CSP1 … 0
The CFI clock source PDC (CMD1:CSS = 0) or DCL (CMD1:CSS = 1) can be divided by
a factor of 1, 1.5 or 2 in order to obtain the CFI reference clock CRCL (see table 32).
Note that in CFI mode 2, the frequency of RCL is only half the CFI data rate.
Table 32
Prescaler Divisors
CSP1
0
0
1
1
Semiconductor Group
DCL
FSC
®
Clock Sources for the CFI and PCM Interfaces if CMD1:CSS = 1
C
F
I
Bit Shift
CTAR
CBSR : CDS2...0
CFI Frame Sync.
CFI Data Rate
÷1.5
÷2
CMD : CSP1, 0
M
U
X
CRCL
CSP0
0
1
0
1
÷4
÷2
÷2
CFI Mode
CFI Mode
0
3
0
3
2
1
2
1
ELIC
216
Internal Reference
Clock (RCL)
R
Bit Shift
POFU
POFD
PCSR
Prescaler Divisor
2
1.5
1
not allowed
PCM Frame Sync.
PCM Data Rate
PMOD : PCR
M
U
X
Application Hints
÷2
PEB 20550
PEF 20550
ITS08046
P
C
M
PDC
PFS
01.96
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