PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 93

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

direction is also referred to as the upstream direction, whereas the receive direction is
referred to as the downstream direction.
Data is transmitted and received at normal TTL / CMOS-levels, the output drivers being
of the tristate type. Unassigned time slots may be either be tristated, or programmed to
transmit a defined idle value. The selection of the states "high impedance" and "idle
value" can be performed with a two bit resolution. This tristate capability allows several
devices to be connected together for concentrator functions. If the output driver
capability of the EPIC-1 should prove to be insufficient for a specific application, an
external driver controlled by the TSC# can be connected.
The PCM-standby function makes it possible to switch all PCM-output lines to high
impedance with a single command. Internally, the device still works normally. Only the
output drivers are switched off.
The number of time slots per 8-kHz frame is programmable in a wide range (from 4 to
128). In other words, the PCM-data rate can range between 256 kbit/s up to
8192 kbit/s. Since the overall switching capacity is limited to 128 time slots per direction,
the number of PCM-ports also depends on the required number of time slots: in case of
32 time slots per frame (2048 kbit/s) for example, four highways are available, in case of
128 time slots per frame (8192 kbit/s), only one highway is available.
The partitioning between number of ports and number of bits per frame is defined by the
PCM-mode. There are four PCM-modes.
The timing characteristics at the PCM-interface (data rate, bit shift, etc.) can be varied in
a wide range, but they are the same for each of the four PCM-ports, i.e. if a data rate of
2048 kbit/s is selected, all four ports run at this data rate of 2048 kbit/s.
The PCM-interface has to be clocked with a PCM-Data Clock (PDC) signal having a
frequency equal to or twice the selected PCM-data rate. In single clock rate operation,
a frame consisting of 32 time slots, for example, requires a PDC of 2048 kHz. In double
clock rate operation, however, the same frame structure would require a PDC of
4096 kHz.
For the synchronization of the time slot structure to an external PCM-system, a PCM-
Framing Signal (PFS) must be applied. The EPIC-1 evaluates the rising PFS edge to
reset the internal time slot counters. In order to adapt the PFS-timing to different timing
requirements, the EPIC-1 can latch the PFS-signal with either the rising or the falling
PDC- edge. The PFS-signal defines the position of the first bit of the internal PCM-frame.
to the PCM-back plane. Due to its capability to dynamically switch the 16-kbit/s
D-channel, the EPIC-1 is one of the fundamental building blocks for networks with either
central, decentral or mixed signaling and packet data handling architecture.
3.5.1
The serial PCM-interface provides up to four duplex ports consisting each of a data
transmit (TxD#), a data receive (RxD#) and a tristate control (TSC#) line. The transmit
Semiconductor Group
PCM-Interface
93
Operational Description
PEB 20550
PEF 20550
01.96