PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 14

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Handling of Layer-1 Functions (EPIC
• Change detection for C/I-channel (IOM-configuration) or feature control
• Additional last-look logic for feature control (SLD-configuration)
• Buffered monitor (IOM-configuration) or signaling channel (SLD-configuration)
Handling of Layer-2 Functions (SACCO)
• Two independent full duplex HDLC-channels
D-channel Multiplexing (D-channel arbiter)
• Serving of multiple subscribers with one HDLC-controller
• Full duplex signaling protocols (e.g. LAPD or proprietary) supported
• Programmable priority scheme
• Broadcast transmission
Line Card Glue Logic
• Power-up reset generator
• Watchdog timer
• Parallel ports (8-bit input, 4-bit I/O)
Boundary Scan Support
• Fully IEEE 1149.1 compatible
• 32-bit device identification register
Bus Interface
• Siemens/Intel or Motorola type P-interface
• 8-bit demultiplexed bus interface
• FIFO-access interrupt or DMA controlled
Semiconductor Group
(SLD-configuration)
– Serial interface
– Protocol support
– 64-bytes FIFO’s per HDLC-channel and direction
Data rate up to 4 Mbit/s
Independent time slot assignment for each channel with programmable time slot
length (1-256 bits)
Support of bus configuration with collision resolution
Continuous transmission of 1 to 32 bytes possible
Auto-mode, fully compatible to PEB 2050 (PBC) protocol
Non-auto mode, address recognition capability
Transparent mode, HDLC-framing only
Extended transparent mode, fully transparent without HDLC-framing
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PEB 20550
PEF 20550
Overview
01.96