PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 90

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

The selection is performed with the EMOD.DMXAD-bit as follows
As a feature of interest to those wishing to use only the EPIC-1 component of the ELIC,
note that in the non-multiplexed mode the OMDR.RBS-bit and the A4-address pin are
internally ORed. In non-multiplexed mode, it is thus possible to tie the A4-address pin
low, and to address the EPIC-1 using the OMDR.RBS-bit and pins A3
interrupt status registers is provided.
When using the Siemens / Intel multiplexed interface, the ELIC can be addressed
– either with even addresses only (i.e. AD0 always 0), which allows data always to be
– or with even and odd addresses, so that the address range does not extend past 7F
Note: It is recommended to tie unused input pins to a defined voltage level.
3.2
The ELIC-signals events that the P should know about immediately by emitting an
interrupt request on the INT-line. To indicate the detailed cause of the request a tree of
Figure 46
ELIC
Semiconductor Group
transferred in the low data byte,
DMXAD = 1
DMXAD = 0
®
Interrupt Structure
Interrupt Structure and Logic
MASK_E
ISTA_E
Watchdog Timer
D-Channel Arbiter
even addresses only,
reduced address range (same addresses as in DEMUX mode).
IWD
IDA
EPIC
IEP
R
EXB
HDLC Channel B, Extended
ICB EXA ICA
HDLC Channel B
90
HDLC Channel A, Extended
HDLC Channel A
ISTA
MASK
Operational Description
ITD05843
ISTA_A
MASK_A
EXIR_A
ISTA_B
MASK_B
EXIR_B
A0.
PEB 20550
PEF 20550
01.96
H
.