PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 27
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
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D-channel processing is supported by multiple different architectures:
1.6.1.2 Decentralized D-Channel Processing, Multiplexed HDLC-Controller.
Typically the D-channel load has a very bursty characteristic. Taking this into account,
the ELIC provides the capability to multiplex one HDLC-controller among several
subscribers. This feature results in a drastical reduction of hardware requirements while
maintaining all benefits of HDLC based signaling.
A D-channel arbiter is used to assign the receive and transmit HDLC-channel
independently to the subscriber terminals.
In downstream direction the arbiter links the transmit channel to one or more (broadcast)
programmable IOM-2 D-channels (ports).
In upstream direction the arbiter assigns the HDLC-receive channel to a requesting
subscriber and indicates to all other subscribers that their D-channels are blocked, using
a control channel.
This configuration supports full duplex layer-2 protocols with bus capability e.g. LAPD or
proprietary implementations. Consequently no polling overhead is necessary providing
the full 16-kbit/s bandwidth of the D-channel for data exchange.
Figure 7
D-Channel Handling with a Multiplexed HDLC-controller
Semiconductor Group
IOM -2
Interface
µP
R
D Channel
27
SACCO CH-A
SACCO CH-B
B Channels
ARBITER
D Channel
Controlling
ELIC
EPIC
R
R
ITS05808
PCM
Highway
Signaling
Highway
PEB 20550
PEF 20550
Overview
01.96
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