OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 13
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
Table 6.
Name
SYSMEMREMAP
PRESETCTRL
SYSPLLCTRL
SYSPLLSTAT
-
SYSOSCCTRL
WDTOSCCTRL
IRCCTRL
-
SYSRESSTAT
-
SYSPLLCLKSEL
SYSPLLCLKUEN
-
MAINCLKSEL
MAINCLKUEN
SYSAHBCLKDIV
-
SYSAHBCLKCTRL
-
-
SSPCLKDIV
UART0CLKDIV
UART1CLKDIV
RTCCLKDIV
-
CLKOUTCLKSEL
CLKOUTUEN
CLKOUTDIV
-
PIOPORCAP0
PIOPORCAP1
Register overview: system control block (base address 0x4004 8000)
All information provided in this document is subject to legal disclaimers.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access Address
R/W
R/W
R
-
R/W
-
R/W
-
R/W
R/W
-
R/W
-
-
-
R/W
R/W
-
R/W
R/W
R/W
-
R
R
Rev. 1 — 15 February 2011
offset
0x000
0x004
0x008
0x00C
0x010 -
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034 -
0x03C
0x040
0x044
0x048 -
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084 -
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4-
0x0DC
0x0E0
0x0E4
0x0E8
0x0EC -
0x0FC
0x100
0x104
Chapter 4: LPC122x System control (SYSCON)
Description
System memory remap
Peripheral reset control and flash
timing overwrite
System PLL control
System PLL status
Reserved
System oscillator control
Watchdog oscillator control
IRC control
Reserved
System reset status register
Reserved
System PLL clock source select
System PLL clock source update
enable
Reserved
Main clock source select
Main clock source update enable
System AHB clock divider
Reserved
System AHB clock control
Reserved
Reserved
SSP clock divder
UART0 clock divider
UART1 clock divider
RTC clock divider
Reserved
CLKOUT clock source select
CLKOUT clock source update
enable
CLKOUT clock divider
Reserved
POR captured PIO status 0
POR captured PIO status 1
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000 0000
0x0000 FFFF
0x0000 0000
0x0000 0000
-
0x0000 0000
0x0000 0000
0x0000 0080
-
0x0000 0000
-
0x0000 0000
0x0000 0000
-
0x0000 0000
0x0000 0000
0x0000 0001
-
0xF01F FFFF
-
-
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
-
0x0000 0000
0x0000 0000
0x0000 0000
-
user
dependent
user
dependent
13 of 442
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