OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 405

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.7.5.3 Restrictions
25.4.7.5.4 Condition flags
25.4.7.5.5 Examples
25.4.7.6.1 Syntax
25.4.7.6.2 Operation
25.4.7.6.3 Restrictions
25.4.7.6.4 Condition flags
25.4.7.6.5 Examples
25.4.7.7.1 Syntax
25.4.7.6 MRS
25.4.7.7 MSR
There are no restrictions.
This instruction does not change the flags.
Move the contents of a special register to a general-purpose register.
MRS Rd, spec_reg
where:
MRS stores the contents of a special-purpose register to a general-purpose register. The
MRS instruction can be combined with the MR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See
In this instruction, Rd must not be SP or PC.
This instruction does not change the flags.
Move the contents of a general-purpose register into the specified special register.
MSR spec_reg, Rn
where:
Rd is the general-purpose destination register.
spec_reg is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
Rn is the general-purpose source register.
ISB ; Instruction Synchronisation Barrier
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
Section
25–25.4.7.7.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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