OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 148

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
9.5.12 UART Auto-baud Control Register
9.5.11 UART Scratch Pad Register
Table 150: UART Modem Status Register (MSR - address 0x4000 8018) bit description
The SCR has no effect on the UART operation. This register can be written and/or read at
user’s discretion. There is no provision in the interrupt interface that would indicate to the
host that a read or write of the SCR has occurred.
Table 151. UART Scratch Pad Register (SCR - address 0x4000 801C) bit description
The UART Auto-baud Control Register (ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Bit
0
1
2
3
4
5
6
7
31:8
Bit Symbol Description
7:0 PAD
31:
8
-
Symbol
DCTS
DDSR
TERI
DDCD
CTS
DSR
RI
DCD
-
A readable, writable byte.
Reserved
All information provided in this document is subject to legal disclaimers.
Value Description
-
0
1
0
1
0
1
0
1
Rev. 1 — 15 February 2011
Delta CTS.
Set upon state change of input CTS. Cleared on an MSR
read.
No change detected on modem input, CTS.
State change detected on modem input, CTS.
Delta DSR.
Set upon state change of input DSR. Cleared on an MSR
read.
No change detected on modem input, DSR.
State change detected on modem input, DSR.
Trailing Edge RI.
Set upon low to high transition of input RI. Cleared on an
MSR read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Delta DCD. Set upon state change of input DCD. Cleared on
an MSR read.
No change detected on modem input, DCD.
State change detected on modem input, DCD.
Clear To Send State. Complement of input signal CTS. This
bit is connected to MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR.
This bit is connected to MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is
connected to MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This
bit is connected to MCR[3] in modem loopback mode.
Reserved, the value read from a reserved bit is not defined. NA
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0x00
-
148 of 442
Reset
value
0
0
0
0
0
0
0
0