OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 436
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
Chapter 11: LPC122x I2C-bus controller
11.1
11.2
11.3
11.4
11.5
11.5.1
11.6
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.5.1
11.7.6
11.7.7
11.7.7.1
11.7.7.2
11.7.8
11.7.9
11.7.10
11.8
11.8.1
11.8.2
11.8.3
11.8.4
11.9
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
11.9.6
11.9.7
11.9.8
11.9.9
11.9.10
11.10
11.10.1
11.10.2
11.10.3
11.10.4
11.10.5
11.10.6
11.10.6.1 STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . . . 212
UM10441
User manual
How to read this chapter . . . . . . . . . . . . . . . . 180
Basic configuration . . . . . . . . . . . . . . . . . . . . 180
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 182
Register description . . . . . . . . . . . . . . . . . . . 182
I
I
Details of I
2
2
C operating modes . . . . . . . . . . . . . . . . . . . 190
C implementation and operation . . . . . . . . 194
I
I
183
I
I
I
0x4000 000C) . . . . . . . . . . . . . . . . . . . . . . . . 185
I
(SCLH - 0x4000 0010 and I2SCLL-
0x4000 0014) . . . . . . . . . . . . . . . . . . . . . . . . 186
Selecting the appropriate I
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
I
0x4000 0018) . . . . . . . . . . . . . . . . . . . . . . . . 187
I
Interrupt in Monitor mode . . . . . . . . . . . . . . . 188
Loss of arbitration in Monitor mode . . . . . . . 189
I
0x4000 00[20, 24, 28]) . . . . . . . . . . . . . . . . . 189
I
0x4000 002C) . . . . . . . . . . . . . . . . . . . . . . . . 189
I
0x4000 00[30, 34, 38, 3C]) . . . . . . . . . . . . . . 190
Master Transmitter mode . . . . . . . . . . . . . . . 190
Master Receiver mode . . . . . . . . . . . . . . . . . 191
Slave Receiver mode . . . . . . . . . . . . . . . . . . 193
Slave Transmitter mode . . . . . . . . . . . . . . . . 193
Input filters and output stages. . . . . . . . . . . . 195
Address Registers, ADR0 to ADR3 . . . . . . . 196
Address mask registers, MASK0 to MASK3. 196
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 196
Shift register, DAT. . . . . . . . . . . . . . . . . . . . . 196
Arbitration and synchronization logic . . . . . . 196
Serial clock generator . . . . . . . . . . . . . . . . . . 197
Timing and control . . . . . . . . . . . . . . . . . . . . 198
Control register, CONSET and CONCLR . . . 198
Status decoder and status register . . . . . . . . 198
Master Transmitter mode . . . . . . . . . . . . . . . 200
Master Receiver mode . . . . . . . . . . . . . . . . . 202
Slave Receiver mode . . . . . . . . . . . . . . . . . . 204
Slave Transmitter mode . . . . . . . . . . . . . . . . 206
Detailed state tables . . . . . . . . . . . . . . . . . . . 207
Miscellaneous states . . . . . . . . . . . . . . . . . . 212
2
2
2
2
2
2
2
2
2
2
2
C Fast-mode Plus . . . . . . . . . . . . . . . . . . . 181
C Control Set register (CONSET - 0x4000 0000)
C Status register (STAT - 0x4000 0004). . . 185
C Data register (DAT - 0x4000 0008). . . . . 185
C Slave Address register 0 (ADR0-
C SCL HIGH and LOW duty cycle registers
C Control Clear register (CONCLR -
C Monitor mode control register . . . . . . . . 187
C Slave Address registers (ADR[1, 2, 3]-
C Data buffer register (DATA_BUFFER -
C Mask registers (MASK[0, 1, 2, 3] -
2
C operating modes. . . . . . . . . . . 199
2
C data rate and duty
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
11.10.6.2 STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . . 212
11.10.7
11.10.7.1 Simultaneous repeated START conditions from
11.10.7.2 Data transfer after loss of arbitration . . . . . . 213
11.10.7.3 Forced access to the I
11.10.7.4 I
11.10.7.5 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
11.10.8
11.10.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 215
11.10.8.2 I
11.10.8.3 The state service routines . . . . . . . . . . . . . . 215
11.10.8.4 Adapting state services to an application. . . 215
11.11
11.11.1
11.11.2
11.11.3
11.11.4
11.11.5
11.11.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 216
11.11.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 217
11.11.5.3 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.11.5.4 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.11.6
11.11.6.1 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.11.6.2 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.11.6.3 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.11.6.4 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.11.6.5 State: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.11.7
11.11.7.1 State: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 218
11.11.7.2 State: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.11.7.3 State: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.11.7.4 State: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.11.8
11.11.8.1 State: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 219
11.11.8.2 State: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.11.8.3 State: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.11.8.4 State: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.11.8.5 State: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 220
11.11.8.6 State: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.11.8.7 State: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.11.8.8 State: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.11.8.9 State: 0xA0. . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.11.9
11.11.9.1 State: 0xA8. . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.11.9.2 State: 0xB0. . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.11.9.3 State: 0xB8. . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.11.9.4 State: 0xC0 . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.11.9.5 State: 0xC8 . . . . . . . . . . . . . . . . . . . . . . . . . 222
Software example . . . . . . . . . . . . . . . . . . . . . 216
Some special cases . . . . . . . . . . . . . . . . . . . 212
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 213
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
I
Initialization routine . . . . . . . . . . . . . . . . . . . 216
Start Master Transmit function . . . . . . . . . . . 216
Start Master Receive function . . . . . . . . . . . 216
I
Non mode specific states. . . . . . . . . . . . . . . 216
Master Transmitter states . . . . . . . . . . . . . . 217
Master Receive states . . . . . . . . . . . . . . . . . 218
Slave Receiver states . . . . . . . . . . . . . . . . . 219
Slave Transmitter states . . . . . . . . . . . . . . . 221
2
2
2
2
C-bus obstructed by a LOW level on SCL or
C state service routines . . . . . . . . . . . . . . . 215
C interrupt service . . . . . . . . . . . . . . . . . . . 215
C interrupt routine . . . . . . . . . . . . . . . . . . . 216
Chapter 26: Supplementary information
2
C-bus. . . . . . . . . . . . 213
UM10441
© NXP B.V. 2011. All rights reserved.
436 of 442
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