OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 46

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
4.6 Reset
4.7 Power management
UM10441
User manual
4.7.1.1 Power configuration in Active mode
4.7.1 Active mode
Reset has four sources on the LPC122x: the RESET pin, Watchdog Reset, Power-On
Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset.
The RESET pin is a Schmitt trigger input pin. Assertion of Reset by any source, once the
operating voltage attains a usable level, starts the IRC causing reset to remain asserted
until the external Reset is de-asserted, the oscillator is running, and the flash controller
has completed its initialization.
On the assertion of a reset source external to the Cortex-M0 CPU (POR, BOD reset,
External reset, and Watchdog reset), the following processes are initiated:
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The LPC122x support a variety of power control features. In Active mode, when the
microcontroller is running, power and clocks to selected peripherals can be optimized for
power consumption. In addition, there are three special modes of processor power
reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode.
Remark: The Debug mode is not supported in Sleep, Deep-sleep, or Deep power-down
modes.
In Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock,
and peripherals are clocked by the system clock or a dedicated peripheral clock.
The microcontroller is in Active mode after reset and the default power configuration is
determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The
power configuration can be changed during run time.
Power consumption in Active mode is determined by the following configuration choices:
1. The IRC starts up. After the IRC-start-up time (maximum of 6 μs on power-up), the
2. The boot code in the ROM starts. The boot code performs the boot tasks and may
3. The flash is powered up. This takes approximately <tbd> μs. Then the flash
•
•
IRC provides a stable clock output.
jump to the flash.
initialization sequence is started, which takes about <tbd> cycles.
The SYSAHBCLKCTRL register controls which memories and peripherals are
running
The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and
the flash block) can be controlled at any time individually through the PDRUNCFG
register
(Table
(Table
All information provided in this document is subject to legal disclaimers.
21).
50).
Rev. 1 — 15 February 2011
Chapter 4: LPC122x System control (SYSCON)
UM10441
© NXP B.V. 2011. All rights reserved.
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