OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 239
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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13.5 Description
13.6 Pin description
13.7 Register description
UM10441
User manual
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, two match registers can be used to provide a single-edge controlled PWM
output on the match output pins. It is recommended to use the match registers that are not
pinned out to control the PWM cycle length.
Remark: The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are
functionally identical except for the peripheral base address.
Table 216
Table 216. Counter/timer pin description
In addition, the level and edge outputs of the two comparators are internally connected to
the remaining capture channels 2 and 3 of each of the 16-bit counter/timers (see
Table
Table 217. Comparator connections to the 16-bit counter/timer
The 16-bit counter/timer0 contains the registers shown in
counter/timer1 contains the registers shown in
follow.
Pin
CT16B0_CAP[1:0]
CT16B1_CAP[1:0]
CT16B0_MAT[1:0]
CT16B1_MAT[1:0]
Comparator output
Comparator 0, level output
Comparator 0, edge output
Comparator 1, level output
Comparator 1, edge output
217). For details on the comparator outputs, see
gives a brief summary of each of the counter/timer related pins.
All information provided in this document is subject to legal disclaimers.
Type
Input
Output
Rev. 1 — 15 February 2011
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
Description
Capture Signal:
A transition on a capture pin can be configured to load the
Capture Register with the value in the counter/timer and
optionally generate an interrupt.
Counter/Timer block can select a capture signal as a clock
source instead of the PCLK derived clock. For more details see
Section
External Match Outputs of CT16B0/1:
When a match register of CT16B0/1 (MR1:0) equals the timer
counter (TC), this output can either toggle, go LOW, go HIGH, or
do nothing. The External Match Register (EMR) and the PWM
Control Register (PWMCON) control the functionality of this
output.
13.7.11.
Timer capture input
CT16B0_CAP2
CT16B0_CAP3
CT16B1_CAP2
CT16B1_CAP3
Table
219. More detailed descriptions
Section
Table 218
18.7.5.
and the 16-bit
UM10441
© NXP B.V. 2011. All rights reserved.
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