OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 83
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
Table 80.
Bit
4
5
6
7
8
9
10
12:11
15:13
31:16
Symbol
MODE
-
INV
-
-
DRV
OD
S_MODE
CLK_DIV
-
PIO0_2 register (PIO0_2, address 0x4004 404C) bit description
…continued
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
-
Rev. 1 — 15 February 2011
Description
Selects function mode (on-chip pull-up resistor control).
Inactive (pull-up resistor not enabled).
Pull-up resistor enabled.
Reserved.
Invert input
Input not inverted.
Input inverted.
Reserved.
Reserved.
Drive current mode (Normal-drive pin).
Low mode current selected.
High mode current selected.
Open-drain mode.
Open-drain mode disabled.
Open-drain mode enabled.
Sample mode
Bypass input filter.
Input pulses shorter than one filter clock are rejected.
Input pulses shorter than two filter clocks are rejected.
Input pulses shorter than three filter clocks are rejected.
Select peripheral clock divider for input filter sampling clock.
IOCONFIGCLKDIV0.
IOCONFIGCLKDIV1.
IOCONFIGCLKDIV2.
IOCONFIGCLKDIV3.
IOCONFIGCLKDIV4.
IOCONFIGCLKDIV5.
IOCONFIGCLKDIV6.
Reserved.
Chapter 6: LPC122x I/O configuration (IOCONFIG)
UM10441
© NXP B.V. 2011. All rights reserved.
83 of 442
Reset
value
1
0
0
1
0
0
0
00
000
0
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