OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 56

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
5.3.2 General purpose registers 0 to 3
5.3.3 System configuration register
Table 56.
The general purpose registers retain data through the Deep power-down mode when
power is still applied to the V
Only a “cold” boot when all power has been completely removed from the chip will reset
the general purpose registers.
Table 57.
This register controls the clock input to the RTC and the hysteresis of the WAKEUP pin.
delayed 1 Hz clock, and the 1 kHz clock. In addition, the peripheral RTC clock, which is
derived from the main clock by the RTC clock divider, can be selected as RTC clock
source.
Remark: The RTC clock source must be selected before the RTC is enabled in the
SYSAHBCLKCTRL register (see
the RTC is running.
Remark: If the external voltage applied on pin V
hysteresis of the WAKEUP input pin has to be disabled in order for the chip to wake up
from Deep power-down mode.
Bit
8
10:9
11
31:12
Bit
31:0
Three clocks can be selected from the 32 kHz RTC oscillator: the 1 Hz clock (default), the
Symbol
SLEEPFLAG
-
DPDFLAG
-
Symbol
GPDATA
General purpose registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to
0x4003 8010) bit description
Power control register (PCON, address 0x4003 8000) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
-
-
Rev. 1 — 15 February 2011
DD(3V3)
Description
Data retained during Deep power-down mode.
Description
Sleep mode flag
Read: No power-down mode entered. LPC122x is in Run
mode.
Write: No effect.
Read: Sleep/Deep-sleep or Deep power-down mode
entered.
Write: Writing a 1 clears the SLEEPFLAG bit to 0.
Reserved. Do not write ones to this bit.
Deep power-down flag
Read: Deep power-down mode not entered.
Write: No effect.
Read: Deep power-down mode entered.
Write: Clear the Deep power-down flag.
Reserved. Do not write ones to this bit.
Table
pin but the chip has entered Deep power-down mode.
21). The clock source must not be changed while
Chapter 5: LPC122x Power Monitor Unit (PMU)
DD(3V3)
drops below <tbd> V, the
UM10441
© NXP B.V. 2011. All rights reserved.
…continued
Reset
value
0x0
56 of 442
Reset
value
0
0x0
0x0
0x0
0x0
0x0