OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 183

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 181. Register overview: I
[1]
UM10441
User manual
Name
ADR3
DATA_
BUFFER
MASK0
MASK1
MASK2
MASK3
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
11.7.1 I
Access Address
R/W
RO
R/W
R/W
R/W
R/W
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 182. I
I2EN I
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I
interface is disabled.
Bit Symbol
1:0 -
2
3
4
5
6
7
31:
8
2
offset
0x028
0x02C
0x030
0x034
0x038
0x03C
C Control Set register (CONSET - 0x4000 0000)
AA
SI
STO
STA
I2EN
-
-
2
C Interface Enable. When I2EN is 1, the I
2
C (base address 0x4000 0000)
2
C Control Set register (CONSET - address 0x4000 0000) bit description
Description
I2C Slave Address Register 3. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Data buffer register. The contents of the 8 MSBs of the I2DAT shift
register will be transferred to the DATA_BUFFER automatically after
every nine bits (8 bits of data plus ACK or NACK) has been received on
the bus.
I2C Slave address mask register 0. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 1. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 2. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 3. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge flag.
I
STOP flag.
START flag.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Reserved
2
2
2
C interrupt flag.
C interface enable.
C interface. Writing a one to a bit of this register causes the
Rev. 1 — 15 February 2011
2
C control register to be set. Writing a zero has no effect.
2
C interface in slave mode, and is not used in master
…continued
Chapter 11: LPC122x I2C-bus controller
2
C interface is enabled. I2EN can be
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
NA
0
0
0
0
NA
-
Reset
value
0x00
0x00
0x00
0x00
0x00
0x00
183 of 442
2
[1]
C