OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 370

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.3.3.3 Exception handlers
25.3.3.4 Vector table
Table 361. Properties of different exception types
[1]
[2]
[3]
[4]
For an asynchronous exception, other than reset, the processor can execute additional
instructions between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that
configurable priority, see
For more information about HardFaults, see
The processor handles exceptions using:
Interrupt Service Routines (ISRs) — Interrupts IRQ0 to IRQ31 are the exceptions
handled by ISRs.
Fault handler — HardFault is the only exception handled by the fault handler.
System handlers — NMI, PendSV, SVCall SysTick, and HardFault are all system
exceptions handled by system handlers.
The vector table contains the reset value of the stack pointer, and the start addresses,
also called exception vectors, for all exception handlers.
the exception vectors in the vector table. The least-significant bit of each vector must be 1,
indicating that the exception handler is written in Thumb code.
Exception
number
14
15
16 and above
To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for
exceptions other than interrupts. The IPSR returns the Exception number, see
See
See
Increasing in steps of 4.
Section 25.3.3.4
Section
[1]
25–25.5.2.6.
All information provided in this document is subject to legal disclaimers.
IRQ
number
-2
-1
0 and above
for more information.
Rev. 1 — 15 February 2011
Section
[1]
25–25.5.2.3.
Exception
type
PendSV
SysTick
Interrupt (IRQ)
Chapter 25: LPC122x Appendix ARM Cortex-M0
Section
Table 25–361
25–25.3.4.
Priority
Configurable
Configurable
Configurable
Figure 25–66
shows as having
[3]
[3]
[3]
Table
UM10441
shows the order of
© NXP B.V. 2011. All rights reserved.
25–356.
Vector
address
0x00000038
0x0000003C
0x00000040 and
above
[4]
[2]
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