OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 415

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.5.3.3 Interrupt Control and State Register
Table 383. CPUID register bit assignments
The ICSR:
See the register summary in
are:
Bits
[31:24]
[23:20]
[19:16]
[15:4]
[3:0]
•
•
provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
indicates:
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
– whether any interrupts are pending.
Name
Implementer
Variant
Constant
Partno
Revision
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Table 25–382
Function
Implementer code:
0x41 = ARM
Variant number, the r value in the rnpn product revision
identifier:
0x0 = Revision 0
Constant that defines the architecture of the processor:, reads
as
0xC = ARMv6-M architecture
Part number of the processor:
0xC20 = Cortex-M0
Revision number, the p value in the rnpn product revision
identifier:
0x0 = Patch 0
Chapter 25: LPC122x Appendix ARM Cortex-M0
for the ICSR attributes. The bit assignments
UM10441
© NXP B.V. 2011. All rights reserved.
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