OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 202

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
11.10.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see
START condition has been transmitted, the interrupt service routine must load DAT with
the 7-bit slave address and the data direction bit (SLA+R). The SI bit in CON must then be
cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in
a repeated START condition (state 0x10), the I
transmitter mode by loading DAT with SLA+W.
Figure
23). The transfer is initialized as in the master transmitter mode. When the
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
2
Chapter 11: LPC122x I2C-bus controller
C block may switch to the master
UM10441
© NXP B.V. 2011. All rights reserved.
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