OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 261

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 243: Capture Control Register (CCR, address 0x4001 8028 (CT32B0) and 0x4001 C028 (CT32B1)) bit
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User manual
Bit
0
1
2
3
4
5
6
7
8
Symbol
CAP0RE 1
CAP0FE
CAP0I
CAP1RE
CAP1FE
CAP1I
CAP2RE
CAP2FE
CAP2I
description
14.7.8 Capture Control Register (CCR and CCR)
Value Description
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, “n” represents the Timer number, 0 or 1.
Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
Enabled.
Disabled.
Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will
generate an interrupt.
Enabled.
Disabled.
Capture on CT32Bn_CAP2 rising edge: a sequence of 0 then 1 on CT32Bn_CAP2 will
cause CR2 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on CT32Bn_CAP2 falling edge: a sequence of 1 then 0 on CT32Bn_CAP2 will
cause CR2 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on CT32Bn_CAP2 event: a CR2 load due to a CT32Bn_CAP2 event will
generate an interrupt.
Enabled.
Disabled.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
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© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0
0