OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 223

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

12.1 How to read this chapter
12.2 Basic configuration
12.3 Features
12.4 Description
UM10441
User manual
The SSP controller is available on all LPC122x parts.
Clocks and power to the SSP are controlled by:
The SSP_PCLK clock can be disabled in the SSP registers (see
can be disabled through the System AHB clock control register bit 11 (see
power savings.
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bit to 16 bit of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
1. The SYSAHBCLKCTRL register (see
2. The SSP_PCLK which is enabled in the SSP clock divider register (see
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UM10441
Chapter 12: LPC122x SSP controller
Rev. 1 — 15 February 2011
This clock is used by the SSP prescale divider.
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
Synchronous Serial Communication
Master or slave operation
Eight-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Table
21).
Table
22). The SSP block
© NXP B.V. 2011. All rights reserved.
Table
User manual
Table
21) for
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22).