OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 17

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.3 System PLL control register
4.5.4 System PLL status register
Table 9.
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and memories. The PLL can
produce a clock up to the maximum allowed for the CPU.
Table 10.
This register is a Read-only register and supplies the PLL lock status (see
Section
Table 11.
Bit
15
31:16
Bit
4:0
6:5
31:7
Bit
0
31:1
Symbol
FLASH_OVERRIDE
-
Symbol
MSEL
PSEL
-
Symbol
LOCK
-
4.10.1).
Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
Value
0
1
-
-
Rev. 1 — 15 February 2011
Description
Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32
Post divider ratio P. The division ratio is 2 × P.
P = 1
P = 2
P = 4
P = 8
Reserved
Description
PLL lock status
PLL not locked
PLL locked
Reserved
Value
0
1
-
Description
access. At higher operating frequencies the
multi-cycle read mode must be used to allow 2, 3,
4, or 5-cycle read configuration. If multi-cycle read
mode is selected, the number of cycles can be
configured in the FLASHCFG register (see
Table
Flash multi-cycle read mode.
Flash 1-cycle read mode.
Flash read mode. The default is 1-cycle flash read
Reserved
Chapter 4: LPC122x System control (SYSCON)
52).
UM10441
© NXP B.V. 2011. All rights reserved.
17 of 442
Reset
value
1
-
Reset
value
00000
00
0x00
Reset
value
0
0x00