OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 58
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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6.1 How to read this chapter
6.2 Features
6.3 General description
UM10441
User manual
6.3.1 Pin function
6.3.2 Pin mode
Each pin has one IOCON register assigned. IOCON registers for pins not available are
reserved (see
available on 64-pin packages.
Table 59.
The I/O configuration registers control the electrical characteristics of the pads. The
following features are programmable:
The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a
peripheral function. If the pins are configured as GPIO pins, the DIR registers determine
whether the pin is configured as an input or output (see
function, the pin direction is controlled automatically depending on the pin’s functionality.
The GPIOnDIR registers have no effect for peripheral functions.
The MODE bit in the IOCON register allows enabling or disabling an on-chip pull-up
resistor for each pin. By default all pull-up resistors are enabled except for the I
pins PIO0_10 and PIO0_11, which do not have a programmable pull-up resistor.
Package GPIO0
LQFP48
LQFP64
•
•
•
•
•
•
UM10441
Chapter 6: LPC122x I/O configuration (IOCONFIG)
Rev. 1 — 15 February 2011
Pin function
Pin mode: Internal pull-up resistor enable/disable
Pin drive
Analog input or digital mode for pads hosting the ADC inputs
I
True, programmable open-drain mode for I
2
C-bus mode or GPIO mode for pads hosting the I
PIO0_0 to PIO0_31 PIO1_0 to PIO1_6 -
PIO0_0 to PIO0_31 PIO1_0 to PIO1_6 PIO2_0 to PIO2_15
Available GPIO pins/IOCON registers
Table
All information provided in this document is subject to legal disclaimers.
59). IOCON registers controlling pins of GPIO port 2 are only
Rev. 1 — 15 February 2011
GPIO1
2
C-bus pins
GPIO2
2
C-bus interface
Table
128). For any peripheral
Total GPIO pins/
OCON registers
39
55
© NXP B.V. 2011. All rights reserved.
User manual
2
C-bus
58 of 442
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