OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 388
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
25.4.4.3.3 Restrictions
25.4.4.3.4 Condition flags
25.4.4.3.5 Examples
25.4.4.4.1 Syntax
25.4.4.4.2 Operation
25.4.4.4.3 Restrictions
25.4.4.4.4 Condition flags
25.4.4.4.5 Examples
25.4.4.4 LDR, PC-relative
25.4.4.5 LDM and STM
In these instructions:
These instructions do not change the flags.
Load register (literal) from memory.
LDR Rt, label
where:
Loads the register specified by Rt from the word in memory specified by label.
In these instructions, label must be within 1020 bytes of the current PC and word aligned.
These instructions do not change the flags.
Load and Store Multiple registers.
•
•
Rt is the register to load.
label is a PC-relative expression. See
Rt, Rn, and Rm must only specify R0-R7.
the computed memory address must be divisible by the number of bytes in the load or
store, see
STR
LDRSH R1, [R2, R3]
LDR
LDR
R0, [R5, R1]
R0, LookUpTable
R3, [PC, #100]
Section
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
25–25.4.3.4.
; Load R0 with a word of data from an address
; Load R3 with memory word at (PC + 100).
; Store value of R0 into an address equal to
; Load a halfword from the memory address
; and write to R1.
; labelled as LookUpTable.
Chapter 25: LPC122x Appendix ARM Cortex-M0
; sum of R5 and R1
; specified by (R2 + R3), sign extend to 32-bits
Section
25–25.4.3.5.
UM10441
© NXP B.V. 2011. All rights reserved.
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