OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 442
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OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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25.4.7.6.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 405
25.4.7.6.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 405
25.4.7.6.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
25.4.7.7
25.4.7.7.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
25.4.7.7.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.7.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.7.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.7.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.8
25.4.7.8.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.8.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.8.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.8.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.8.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.9
25.4.7.9.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.9.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
25.4.7.9.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.9.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.9.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.10 SVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.10.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.10.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.10.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.10.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.10.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.11 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.11.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.11.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 407
25.4.7.11.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.11.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.11.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.12 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.12.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.12.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.12.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . 408
Chapter 26: Supplementary information
26.1
26.2
26.3
26.3.1
26.3.2
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 423
References . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Legal information. . . . . . . . . . . . . . . . . . . . . . 424
MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 424
442
25.4.7.12.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . 408
25.4.7.12.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 409
25.5
25.5.1
25.5.2
25.5.2.1
25.5.2.2
25.5.2.3
25.5.2.4
25.5.2.5
25.5.2.6
25.5.2.7
25.5.2.7.1 Hardware and software control of interrupts 413
25.5.2.8
25.5.2.8.1 NVIC programming hints . . . . . . . . . . . . . . . 414
25.5.3
25.5.3.1
25.5.3.2
25.5.3.3
25.5.3.4
25.5.3.5
25.5.3.6
25.5.3.7
25.5.3.7.1 System Handler Priority Register 2 . . . . . . . 419
25.5.3.7.2 System Handler Priority Register 3 . . . . . . . 419
25.5.3.8
25.5.4
25.5.4.1
25.5.4.2
25.5.4.2.1 Calculating the RELOAD value . . . . . . . . . . 421
25.5.4.3
25.5.4.4
25.5.4.5
26.3.3
26.4
26.5
26.6
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
About the ARM Cortex-M0. . . . . . . . . . . . . . 409
Nested Vectored Interrupt Controller . . . . . . 409
Accessing the Cortex-M0 NVIC registers using
CMSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Interrupt Set-enable Register. . . . . . . . . . . . 410
Interrupt Clear-enable Register . . . . . . . . . . 410
Interrupt Set-pending Register. . . . . . . . . . . . 411
Interrupt Clear-pending Register . . . . . . . . . . 411
Interrupt Priority Registers . . . . . . . . . . . . . . 412
Level-sensitive and pulse interrupts. . . . . . . 412
NVIC usage hints and tips . . . . . . . . . . . . . . 413
System Control Block. . . . . . . . . . . . . . . . . . 414
The CMSIS mapping of the Cortex-M0 SCB
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
CPUID Register . . . . . . . . . . . . . . . . . . . . . . 414
Interrupt Control and State Register . . . . . . 415
Application Interrupt and Reset Control
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
System Control Register . . . . . . . . . . . . . . . 418
Configuration and Control Register . . . . . . . 418
System Handler Priority Registers . . . . . . . . 419
SCB usage hints and tips. . . . . . . . . . . . . . . 420
System timer, SysTick . . . . . . . . . . . . . . . . . 420
SysTick Control and Status Register . . . . . . 420
SysTick Reload Value Register . . . . . . . . . . 421
SysTick Current Value Register . . . . . . . . . . 421
SysTick Calibration Value Register . . . . . . . 421
SysTick usage hints and tips . . . . . . . . . . . . 422
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 424
Chapter 26: Supplementary information
Date of release: 15 February 2011
UM10441
Document identifier: UM10441
All rights reserved.
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