OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 383

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
Fig 71. ROR #3
31
25.4.3.4 Address alignment
25.4.3.5 PC-relative expressions
25.4.3.6 Conditional execution
An aligned access is an operation where a word-aligned address is used for a word, or
multiple word access, or where a halfword-aligned address is used for a halfword access.
Byte accesses are always aligned.
There is no support for unaligned accesses on the Cortex-M0 processor. Any attempt to
perform an unaligned memory access operation results in a HardFault exception.
A PC-relative expression or label is a symbol that represents the address of an instruction
or literal data. It is represented in the instruction as the PC value plus or minus a numeric
offset. The assembler calculates the required offset from the label and the address of the
current instruction. If the offset is too big, the assembler produces an error.
Remark:
Most data processing instructions update the condition flags in the Application Program
Status Register (APSR) according to the result of the operation, see
instructions update all flags, and some only update a subset. If a flag is not updated, the
original value is preserved. See the instruction descriptions for the flags they affect.
You can execute a conditional branch instruction, based on the condition flags set in
another instruction, either:
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•
•
•
•
•
If n is 32, then the value of the result is same as the value in Rm, and if the carry flag
is updated, it is updated to bit[31] of Rm.
ROR
ROR
For most instructions, the value of the PC is the address of the current instruction plus
4 bytes.
Your assembler might permit other syntaxes for PC-relative expressions, such as a
label plus or minus a number, or an expression of the form [PC, #imm].
immediately after the instruction that updated the flags
after any number of intervening instructions that have not updated the flags.
with shift length, n, greater than 32 is the same as
with shift length n-32.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
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Chapter 25: LPC122x Appendix ARM Cortex-M0
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UM10441
© NXP B.V. 2011. All rights reserved.
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