OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 401

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.6.1.2 Operation
25.4.6.1.3 Restrictions
25.4.6.1.4 Condition flags
25.4.6.1.5 Examples
BX Rm
BLX Rm
where:
All these instructions cause a branch to the address indicated by label or contained in the
register specified by Rm. In addition:
BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is
suitable for use by a subsequent POP {PC} or BX instruction to perform a successful
return branch.
Table 371
Table 371. Branch ranges
In these instructions:
Remark: Bcond is the only conditional instruction on the Cortex-M0 processor.
These instructions do not change the flags.
Instruction
B label
Bcond label
BL label
BX Rm
BLX Rm
•
•
•
•
cond is an optional condition code, see
label is a PC-relative expression. See
Rm is a register providing the address to branch to.
The BL and BLX instructions write the address of the next instruction to LR, the link
register R14.
The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.
Do not use SP or PC in the BX or BLX instruction.
For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update
the EPSR T-bit and is discarded from the target address.
B
BL
shows the ranges for the various branch instructions.
loopA ; Branch to loopA
All information provided in this document is subject to legal disclaimers.
funC
Rev. 1 — 15 February 2011
; Branch with link (Call) to function funC, return address
; stored in LR
Chapter 25: LPC122x Appendix ARM Cortex-M0
Section
Section
Branch range
−2 KB to +2 KB
−256 bytes to +254 bytes
−16 MB to +16 MB
Any value in register
Any value in register
25–25.4.3.5.
25–25.4.3.6.
UM10441
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